1. Field of the Invention
The present invention relates generally to integrated circuit devices used for processing data through communication networks, and more particularly, to methods and apparatus for implementing data/clock recovery systems in networking circuitry.
2. Description of the Related Art
In view of the recent push to develop faster networking technology, networking companies have been required to design circuitry that is sufficiently fast to process data at increased speeds. As an example, a number of computer network companies have been working on the development of gigabit Ethernet networking products that are in compliance with the IEEE 802.3z standard (1000 Mbps-Gigabit Ethernet). Although there has been significant progress in increasing data transfer rates to gigabit speeds and greater, much of the core circuitry that is currently implemented in Ethernet transceivers is lagging the advancement in other core gigabit Ethernet circuitry.
A core part of a gigabit Ethernet circuit is the physical level circuitry that is used to interface over a physical media to other network devices. As is well known, transceivers that are integrated into the physical level circuitry must have superior speed, processing integrity and integration flexibility with other existing network circuitry. Typically, the transceivers use analog phase locked loop (PLL) circuitry to do the data/clock recovery. The data clock recovery circuit uses a VOC to generate the multiple phase clocks that run at a lower rate than baud rate to over-sample and latch incoming high speed serial data streams. The multiple sampled data is then fed to multiple phase detectors in parallel, and the outputs of the phase detectors drive multiple charge pump circuits. Each of the charge pumps then drive a single analog loop filter. The output of the loop filter then controls a VCO output frequency.
Unfortunately, the conventional analog data/clock recovery circuits are harder to design and difficult to integrate with digital media access controller (MAC) circuitry. In addition, crosstalk between a transmitter's analog PLL and a receiver's analog PLL is known to cause excessive jitter problems when these circuits are integrated with traditional CMOS network circuitry. As a result, the conventional analog PLL solutions introduce performance reducing side effects that make them incompatible with many of today's high speed networking circuit components.
In view of the foregoing, there is a need for a digital data/clock recovery system that is capable of processing data at high speeds.